1. Field of the Invention
The invention relates to a flash memory device, and more particularly, to a flash memory device with a reduced amount of pins and reduced power consumption for reading/writing operations.
2. Description of the Related Art
Flash memory is widely used in electronic products today, especially for portable applications, as a result of its non-volatile and in-system re-programmable characteristics. The basic structure of a flash memory cell includes a control gate, a drain diffusion region and a source diffusion region on a substrate to form a transistor with a floating gate under the control gate for an electron storage device. The channel region lies under the floating gate with a tunnel oxide insulation layer therebetween. The energy barrier of the tunnel oxide can be overcome by applying a sufficiently high enough electric field across the tunnel oxide insulation layer. This allows electrons to pass through the tunnel oxide insulation layer, thus, changing the amount of electrons stored in the floating gate. The amount of electrons stored in the floating gate determines the threshold voltage (Vt) of the cell. More electrons stored in the floating gate causes the cell to have a higher Vt. The Vt of a cell is used to represent stored data of the cell.
With the development of flash memory technology, a flash memory device is now capable of supporting multiple channels of memory modules. Each channel comprises a memory module and is coupled to a set of input/output (I/O) pins (as an example, 8 bits of I/O pins). As the number of channel's increase, the number of I/O pins and control pins, such as the write enable (WE) pins, read enable (RE) pins, write protect (WP) pins, ready/busy (RB) pins . . . etc., are all greatly increased.
Therefore, a novel design for a flash memory device, which may greatly reduce the total number of pins and further reduce power consumption of reading/writing operations, is highly required.